AMD Ryzen Die Shot and Caches Shown at ISSCC



As the launch of AMD Ryzen is getting closer, more and more details start to appear. We know most specs, clock-frequencies and even pricing. However AMD shared some more details about the microarchitecture about Ryzen.

A number of slides have been shown at ISSCC (International Solid-State Circuits Conference) earlier this month, that info likely needed to remain private, but a Japanese website has released three slides and accompanying information which also shows some die shots and (Ry)zen architecture.

Ryzen is now confirmed to be fabbed at Globalfoundries on a 14-nanometer FinFET 3D transistor process. Above you can see a single Ryzen core, that would be exactly one core with your floating point unit and an integer engine. It is completely different towards Bulldozer (two integer engines / one floating point unit per each core). You will spot 64KB Instruction cache and 32 KB data caches (L1). The layout is different and looking at it, this brings Neural Net prediction and efficient branch prediction to mind as explained in our preview. The second slide shows four cores with in-between it one massive L3 cache pool is addressed as a CCX, a Core Complex unit holding 4 cores with that massive shared L3 cache pool.

Then there is a third slide called Zen architecture that discusses SMT, or simultaneous multi-threading. This is what you guys know as Intel’s Hyper-Threading.  Multi-threaded applications can execute threads in parallel, every and any Ryzen core can execute two threads at the same time. For a 4-core processors that obviously is 8 threads, 6-core and 8-cores can simultaneously execute 12 threads and 16 threads, respectively. Well, nothing new there either. The slides also still claim that 40% IPC performance increase ofer last gen products. Combined with the Boost adn Turbos AMD will be applying, it can be a very succesful processor series.