Upcoming Hardware Launches 2021 (Updated Feb 2021) February 9, 2021
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Upcoming Hardware Launches 2021 (Updated Feb 2021)

n this article, which our team will regularly update, we will maintain a growing list of information pertaining to upcoming hardware releases based on leaks and official announcements as we spot them. There will obviously be a ton of rumors on unreleased hardware, and it is our goal to—based on our years of industry experience—exclude the crazy ones. In addition to these upcoming hardware release news, we will regularly adjust the structure of this article to better organize information. Each time an important change is made to this article, it will re-appear on our front page with a “new” banner, and the additions will be documented in the forum comments thread. This article will not leak information we signed an NDA for.

Feel free to share your opinions and tips in the forum comments thread and subscribe to the same thread for updates.

Last Update (Feb 9th):

Older Updates

 

Processors

AMD Lucienne Zen 2 APUs / Ryzen 5000

  • Release Date: probably 2021
  • Successor to “Renoir”
  • Built on Zen 2 CPU cores, but still branded “Ryzen 5000”
  • The model number scheme goes as 5x00U, where if “x” is an odd number, the chip is “Zen 2 Lucienne” based, and if it’s an even number, it is “Zen 3 Cezanne” based
  • Uses Vega iGPU
  • Built on slightly refined 7 nm process, but not N7P or N7+
  • Ryzen 3 5300U: 4c/8t, 2.6 GHz base, 3.85 GHz boost, 4 MB L3, 10-25 W TDP, 6 CU @ 1.5 GHz
  • Ryzen 5 5500U: 6c/12t, 2.1 GHz base, 4.0 GHz boost, 8 MB L3, 10-25 W TDP, 7 CU @ 1.8 GHz
  • Ryzen 7 5700U: 8c/16t, 1.8 GHz base, 4.3 GHz boost, 8 MB L3, 10-25 W TDP, 8 CU @ 1.9 GHz
  • For other Ryzen 5000 U models, check the Cezanne section
  • Built on TSMC 7 nm process, N7
  • Sources

AMD Cézanne Zen 3 APUs / Ryzen 5000

  • Release Date: CES 2021
  • Successor to “Renoir”
  • Built on Zen 3 CPU cores, paired with Vega iGPU
  • The model number scheme goes as 5x00U, where if “x” is an odd number, the chip is “Zen 2 Lucienne” based, and if it’s an even number, it is “Zen 3 Cezanne” based
  • Ryzen 3 5400U: 4c/8t, 2.6 GHz base, 4.0 GHz boost, 8 MB L3, 10-25 W TDP, 6 CU @ 1.6 GHz
  • Ryzen 5 5600U: 6c/12t, 2.3 GHz base, 4.2 GHz boost, 12 MB L3, 10-25 W TDP, 7 CU @ 1.8 GHz
  • Ryzen 5 5600H: 6c/12t, 3.0 GHz base, 4.1 GHz boost, 8 MB L3, 45 W TDP
  • Ryzen 7 5700G: 6c/12t
  • Ryzen 7 5800U: 8c/16t, 2.0 GHz base, 4.4 GHz boost, 16 MB L3, 10-25 W TDP, 8 CU @ 2.0 GHz, Cinebench 1T=1475, nT=7630
  • Ryzen 7 5800H: 8c/16t, 3.2 GHz base, 4.44 GHz boost, 16 MB L3, 45 W, Cinebench 1T=1475, nT=7630
  • Ryzen 7 5800HS: 8c/16t, 3.1 GHz base, 4.5 GHz boost, 16 MB L3, 35 W
  • Ryzen 9 5900HS: 8c/16t, 3.3 GHz base, 4.6 GHz boost, 16 MB L3
  • Ryzen 9 5980HX: 8c/16t
  • For other Ryzen 5000U models, check the Lucienne section
  • Built on slightly refined 7 nm process, but not N7P or N7+
  • Similar core counts as predecessors
  • 19% IPC uplift on Zen 3 models
  • 20 PCIe lanes
  • Die is 10% larger than Renoir, due to larger Zen 3 core design and larger L3 cache
  • Comes in 15 W and 45 W SKUs
  • “Van Gogh” APU is based on Zen 3, too, but uses RDNA2 iGPU for the ultra-low-end
  • Sources

AMD Zen 3 Threadripper “Genesis Peak”

  • Release Date: 2021, possibly announced at CES 2021
  • Codename: Genesis Peak
  • Built on Zen 3 CPU cores
  • Lineup starts with 16 cores, possibly up to 64
  • Unknown if existing TRX40 motherboards are compatible
  • Sources

AMD Zen 3 Server “Milan” [updated]

  • Release Date: Early 2021
  • Built on Zen 3 CPU cores
  • Lineup ranges from 16 to 64 cores + SMT
  • 20% faster than Rome
  • Cinebench R23 of 64c/128t 2P system: 87878 points
  • EPYC 7763, 2.45 GHz, 64c/128t, 256M cache, 280 W, CAD$ 8,069
  • EPYC 7713, 2.0 GHz, 64c/128t, 256M cache, 225 W
  • EPYC 75F3, 3.3 GHz, 32c/64t, 256M cache, 280 W
  • EPYC 7543, 2.8 GHz, 32c/64t, 256M cache, 225 W, CAD$ 2,579
  • EPYC 7413, 2.65 GHz, 24c/48t, 128M cache, 180 W
  • EPYC 7313, 3.0 GHz, 16c/32t, 128M cache, 155 W
  • Sources

AMD Zen 4 [updated]

  • Release Date: Late 2021
  • “In Design” as of Nov 2018
  • “On Track” for 2021 launch as of Dec 9, 2019
  • 5 nm TSMC process
  • DDR5 memory support
  • Improves IPC
  • Server platform codenamed “Genoa”
  • PCI-Express Gen 5
  • More cores per chiplet
  • Uses 3rd generation Infinity Fabric, which adds cache-coherent unified memory
  • Desktop changes socket to AM5
  • Uses Socket SP5 for EPYC
  • Nov 2020 statement from AMD: “Zen 4 is going to have a similar long list of things, where you look at everything from the caches, to the branch prediction, [to] the number of gates in the execution pipeline. Everything is scrutinized to squeeze more performance out.”
  • Adds support for USB 4.0
  • Sources

AMD Zen 5

  • Release Date: 2022
  • 5 nm or 3 nm TSMC process
  • DDR5 memory support
  • PCI-Express Gen 5
  • Desktop codename: “Raphael”
  • APU codename: “Rembrandt”
  • Uses Socket SP5 for server, desktop uses Socket AM5
  • Sources

Intel Ice Lake Server [updated]

  • Release date: 2021
  • Production started as of Jan 2021
  • Ice Lake mobile was launched in late 2019
  • Ice Lake desktop was scrapped because it wasn’t competitive with Comet Lake
  • Xeon codename “Whitley”
  • Uses new 4189-pin LGA socket
  • 8-channel DDR4 interface
  • 10 nanometer DUV (deep-ultraviolet) process
  • Brand-new CPU core design codenamed “Sunny Cove”
  • PCI-Express Gen 4.0
  • “GenuineIntel Family 6 Model 106 Stepping 4” processor: 24c/48t, 2.2 GHz base, 2.9 GHz boost, L1D 48 KB, L1I 32 KB, L2 1.25 MB, L3 36 MB
  • “GenuineIntel Family 6 Model 106 Stepping 5” processor: 28c/56t, 1.5 GHz base, 3.5 GHz boost, L1D 48 KB, L1I 32 KB, L2 1.25 MB, L3 42 MB
  • 2x 28c CPU Geekbench SP = 3424, MP = 38079, EPYC 7742: SP = 4398, MP = 35492
  • A 36c/72t chip was spotted in leaked Geekbench result, so core counts could be higher than 28. 3.6 GHz base, 1.25 MB L2 per core (45 MB total), 54 MB L3 cache
  • Adds AVX512 instructions (so far available only on HEDT platform, since Skylake-X). New instructions: AVX512F, AVX512CD, AVX512DQ, AVX512BW, and AVX512VL. New commands: AVX512_IFMA, and AVX512_VBMI
  • 20–30% broadening of various number crunching resources, wider execution window, more AGUs
  • 18% IPC gains vs. Cascade Lake
  • SHA-NI and Vector-AES instruction sets, up to 75% higher encryption performance vs. “Skylake”
  • Supports unganged memory mode
  • Integrated GPU based on new Gen11 architecture, up to 1 TFLOP/s ALU compute performance
  • Integrated GPU supports DisplayPort 1.4a and DSC for 5K and 8K monitor support
  • Gen11 also features tile-based rendering, one of NVIDIA’s secret-sauce features
  • Integrated GPU supports VESA adaptive V-sync, all AMD FreeSync-capable monitors should work with this
  • Ice Lake introduces Intel TME (Total Memory Encryption), also Intel Platform Firmware Resilience (Intel PFR)
  • Sources

Intel Core i9-10990XE

  • Release Date: unknown, originally early 2020, seems cancelled now
  • 22-cores + HyperThreading
  • Uses Cascade Lake-X architecture
  • LGA2066 Socket
  • 1 MB L2 cache per core, 30.25 MB shared L3 cache
  • 4 GHz base, up to 5 GHz boost
  • Roughly matches Threadripper 3960X in Cinebench
    Sources

Intel Rocket Lake [updated]

  • Release Date: Q1 2021
  • Announcement: CES 2021
  • Succeeds “Comet Lake”
  • Variants: Rocket Lake-“S” (mainstream desktop), -“H” (mainstream notebook), -“U” (ultrabook), and -“Y” (low power portable)
  • “11th Gen Intel Core” processors
  • 14 nanometer production process
  • Tops out at eight cores (two less than 10-core Comet Lake)
  • Some indication of mixed HyperThreading configurations; for example, 8-core, 12-thread
  • Uses “Cypress Cove” core, which is a backport of “Golden Cove” to 14 nm process
  • Up to 22% IPC improvement over Skylake
  • No FIVR, uses SVID VRM architecture
  • 125 W maximum TDP
  • PL1 and PL2 power limits are similar to 10th gen Comet Lake
  • Compatible with 400-series chipsets
  • 500-series chipsets with added features
  • Socket LGA1200 (just like Comet Lake)
  • Supports PCI-Express 4.0
  • 20 PCIe lanes (four more than before)
  • Intel Xe integrated graphics, based on Gen 12 with HDMI 2.0b and DisplayPort 1.4a, HBR3
  • Xe EU count of only 32, Tiger Lake will have 96
  • Deep Learning Boost / VNNI support
  • New media encoders: 4K60 12b 4:4:4 HEVC, VP9, SCC. 10b 4:2:0 AV1
  • 2.5 Gb/s Ethernet, Thunderbolt 4, USB 3.2 20G
  • Memory support: DDR4-3200
  • 32 KB L1I cache, 48 KB L1D cache, 512 KB per core L2 cache, and 16 MB shared L3 cache (8-core chip)
  • Engineering Sample: Family 6, Model 167, Stepping 0, 8c/16t, 3.4 GHz base, 5.0 GHz boost
  • Engineering Sample: Family 6, Model 167, Stepping 0, 8c/16t, 3.4 GHz base, 4.2 GHz boost
  • Engineering Sample: Family 6, Model 167, Stepping 0, 8c/16t, 3.2 GHz base, 4.3 GHz boost
  • Core i9-11900K: 8c/16t, 5.3 GHz single boost, 4.8 GHz all-core boost, 16 MB L3, TVB, 125 W, € 500
  • Core i9-11900 & 11900F: 8c/16t, 65 W, € 408
  • Core i7-11700K: 8c/16t, 5.0 GHz single boost, 4.6 GHz all-core boost, 16 MB L3, 125 W, € 377
  • Core i7-11700KF: 125 W, € 350
  • Core i7-11700 & 11700F: 65 W, € 280
  • Core i5-11600K: 6c/12t, 4.9 GHz single boost, 4.7 GHz all-core boost, 12 MB L3, 125 W, € 240
  • Core i5-11600KF: 6c/12t, 125 W, € 220
  • Core i5-11400: 6c/12t, 4.4 GHz single boost, 4.2 GHz all-core boost, 12 MB L3, 65 W, € 170
  • Core i5-11400F: 65 W, € 146
  • Core i7-11700K PassMark score comparable to Ryzen 7 5800X
  • 11900KF hits all-core boost of 4.8 GHz, but reaches 98°C with 360 mm AIO liquid cooling
  • Sources

Intel Willow Cove and Golden Cove Cores

  • Release Date: 2021
  • Succeeds “Sunny Cove”
  • Willow Cove improves on-die caches, adds more security features, and takes advantage of 10 nm+ process improvements to increase clock speeds versus Sunny Cove
  • Golden Cove will add significant single-thread (IPC) increases over Sunny Cove, add on-die matrix multiplication hardware, improved 5G network-stack HSP performance, and more security features than Willow Cove
  • Sources

Intel Alder Lake [updated]

  • Release Date: Sep 2021
  • Mixes CPU cores of various processing power (and energy consumption), similar to the Big.Little-like designs for mobile devices
  • Combines up to eight Golden Cove with up to eight Gracemont (Atom) cores
  • These cores have two different instruction sets; for example, Golden Cove has AVX-512, TSX-NI, and FP16, which Gracemont lacks
  • 10 nm+ SuperFin process
  • Uses Socket LGA1700
  • Alder Lake for desktop: 37.5 mm x 45 mm package
  • Desktop CPUs come in 125 W and 80 W
  • Could use Foveros 3D Stacking technology
  • Possible CPU configurations 8+8+1 (8 big cores, 8 small cores, GT1 integrated), and 6+0+1 (6 big cores, no small cores and GT1 integrated)
  • Other config is 6 big cores + 8 small cores.
  • Prototype: 16c/32t, 1.8 GHz base, 4.0 GHz boost, 12.5 MB L2, 30 MB L3
  • Includes Gen12 Xe iGPU, running at 1.5 GHz
  • DDR5 memory support, also LPDDR4X
  • Clocks up to 4.7 GHz
  • PCI-Express 5.0 support
  • Includes CLDEMOTE instruction to invalidate cache lines
  • Sources

Intel Sapphire Rapids [updated]

  • Release Date: H2 2021
  • Successor to Cooper Lake
  • 8-channel DDR5
  • Uses Socket LGA4677
  • For enterprise / data center
  • 56 cores, 112 threads using two dies
  • EMIB to connect the dies using an active interposer
  • HBM memory supported
  • 10 nm+ SuperFin production process
  • Willow Cove CPU cores
  • ES clocked at 2 GHz
  • PCIe 5.0
  • CXL 1.1 support
  • Platform name: Eagle Stream
  • Includes CLDEMOTE instruction to invalidate cache lines
  • Sources

Intel Grand Ridge

  • Release Date: 2022 or later
  • Produced on 7 nm HLL+ process
  • Successor to Atom “Snow Ridge”
  • 24 cores across 6 clusters with 4 cores each
  • 4 MB L2 per cluster, plus L3 cache
  • Uses Gracemont CPU core
  • Dual-channel DDR5
  • PCI-Expres Gen 4 with 16 lanes
  • Sources

Intel Elkhart Lake

  • Release Date: unknown
  • Produced on 10 nm process
  • Designed for next-gen Pentium Silver and Celeron processors
  • CPU cores use Tremont architecture
  • GPU uses Gen 11
  • Dual-core and Quad-core configurations
  • Single-channel memory controller with DDR4 and LPDDR4/x support
  • Engineering sample: 1.9 GHz, 5/9/12 W TDP
  • Sources

Intel Meteor Lake

  • Release Date: 2022 or 2023
  • Succeeds “Alder Lake”
  • New microarchitecture, more advanced than “Willow Cove”, possibly “Golden Cove”
  • As of late 2020 Intel is adding support for Meteor Lake to the Linux Kernel
  • Produced on 7 nm EUV Intel process
  • Sources

Intel Jasper Lake

  • Release Date: unknown
  • Uses Tremont architecture
  • 10 nm production process
  • Successor to Gemini Lake
  • ES: 4c/4t, 1.1 GHz Base, 1.12 GHz Boost
  • DDR4 memory support
  • Pentium Silver J6005: 4c/4t, 2 GHz base, 3 GHz boost, 4 MB L2
  • Celeron J5105: 2 GHz vase, 2.8 GHz boost, 4 MB L2
  • Celeron J4505: 2c/2t, 2 GHz base, 2.9 GHz boost 4 MB L2
  • Pentium Silver N6000 Mobile: 4c/4t, 1.1 GHz base, 3.1 GHz boost, 4 MB L2
  • Celeron N5100 Mobile: 1.1 GHz base, 2.8 GHz boost
  • Celeron N4500 Mobile: 2c/2t, 1.1 GHz base, 2.8 GHz boost
  • Sources

Intel Granite Rapids

  • Release Date: 2022
  • Successor to Sapphire Rapids
  • 8-channel DDR5
  • For enterprise / data center
  • PCIe 5.0
  • Probably 7 nm+ process
  • Platform name: Eagle Stream
  • Sources

VIA CenTaur / Zhaoxin KaiXian

  • Release Date: H2 2020
  • Eight-core 64-bit CPU, 2.5 GHz
  • AVX-512 supported
  • 16 nm FinFET TSMC
  • 195 mm² die size
  • Use LGA socket
  • Codename: “CHA”, pronounced “C-H-A”
  • Separate AI co-processor “NCORE”
  • All cores + NCORE connected using a ring bus
  • Integrated VIA S3 graphics with DirectX 11.1
  • 16 MB shared L3 cache
  • Four-channel DDR4-3200 memory support
  • 44 PCI-Express 3.0 lanes
  • Sold as Zhaoxin KaiXian KX-6780A in China (end of Jan 2020): 8 core, 8 threads, 2.7 GHz, 8 MB cache, dual-channel DDR4-3200
  • Southbridge integrated
  • Multi-socket capable
  • Sources

Graphics / GPUs

NVIDIA RTX 3050 / RTX 3050 Ti

  • Release Date: unknown, possibly 2021
  • RTX 3050: 4 GB GDDR6
  • RTX 3050 Ti: 6 GB GDDR6
  • Sources

NVIDIA RTX 3060 [updated]

  • Release Date: Feb 25th
  • MSRP: $329
  • GA106 GPU: 8 nm, 3840 CUDA cores, 30 SM
  • 28 SM and 3584 cores active on RTX 3060
  • 12 GB VRAM, 192-bit, GDDR6
  • 170 W TDP
  • 25 RT TFLOPS
  • Matches RTX 2080 performance
  • Sources

NVIDIA RTX 3060 Ultra

  • Release Date: 2021
  • Same GA104 GPU as RTX 3060 Ti and RTX 3070
  • 12 GB GDDR6
  • 192-bit or 256-bit memory bus
  • $449
  • Sources

NVIDIA RTX 3070 Super / RTX 3080 Super

  • Release Date: 2021
  • No details known
  • Sources

NVIDIA RTX 3070 Ti

  • Release Date: 2021
  • 58 SM, 7424 cores, 320-bit memory, 16 GB VRAM, GDDR6 or GDDR6X
  • Sources

NVIDIA RTX 3080 Ti [updated]

  • Release Date: Apr 2021
  • Another source says pushed back due to supply issues
  • Based on same GA102 GPU as RTX 3080: GA102-250-KD-A1
  • PG133-SKU15 PCB
  • 80 SM, 10240 cores, 80 RT cores, 112 ROPs
  • 12 GB GDDR6X, 384-bit
  • $999
  • Sources

NVIDIA Ampere with more VRAM

  • Release Date: 2021
  • Possibly canceled as of Oct 2020
  • RTX 3080 with 20 GB memory (instead of 10 GB)
  • RTX 3070 with 16 GB memory (instead of 8 GB)
  • Sources

NVIDIA Ampere Refresh

  • Release Date: unknown
  • NVIDIA is moving their existing designs from Samsung 8 nm to TSMC 7 nm
  • Sources

NVIDIA Hopper

  • Release Date: unknown
  • Successor to “Ampere” architecture, or next compute-only architecture
  • MCM (multi-chip module) GPU packages
  • Seems to be for workstation/compute only
  • Sources

NVIDIA Ada Lovelace

  • Release Date: unknown
  • Successor to “Ampere” architecture, possibly gaming-only focused
  • AD102: 18,432 shaders, 144 SMs
  • 5 nanometer process
  • Sources

AMD Radeon RX 5300 XT

  • Release date: unknown
  • Non-XT version has launched on Aug 31, 2020 (1408 cores, 3 GB GDDR6, 96-bit, 1448 MHz game clock, 1645 MHz boost, 100 W TDP)
  • 24 compute units / 1536 stream processors
  • 3 GB GDDR6 memory, 96-bit
  • 7 nanometer production process
  • Probably based on Navi 14 GPU
  • Sources

AMD Radeon RX 5600M and RX 5700M

  • Release date: unknown
  • Based on Navi 10 silicon
  • 7 nanometer production process
  • RX 5700M: 2304 shaders, 144 TMUs, 64 ROPS, 8 GB GDDR6 memory, 256-bit, 1620-1720 MHz
  • RX 5600M: 2304 shaders, 144 TMUs, 64 ROPS, 6 GB GDDR6 memory, 192-bit, 1190-1265 MHz
  • Sources

AMD Radeon RX 6700 & RX 6700 XT [updated]

  • Release date: March 2021
  • Navi 22
  • RX 6700 XT: 40 compute units, 2560 cores, 186-221 W
  • RX 6700: 36 compute units, 2304 cores, 146-156 W
  • Very similar to Navi 10, could be rebranded Navi 10 chip with minor improvements
  • 12 GB 192-bit GDDR6 memory
  • Memory could also be mixed density over 256-bit, i.e. 4x 16 Gbit + 4x 8 Gbit
  • 7 nanometer production process
  • RDNA2 architecture
  • Codename “Navy Flounder”
  • Below $250
  • Sources

AMD Radeon RX 6500

  • Release date: unknown
  • 40 compute units / 2560 stream processors
  • 192-bit GDDR6 memory
  • 7 nanometer production process
  • RDNA2 architecture
  • Codename “Navy Flounder”
  • Below $250
  • Sources
  • Release date: unknown, probably 2022 or late 2021
  • Dual-chiplet design
  • Uses RDNA3 architecture
  • Each chiplet has 80 CU / 5120 cores
  • Total 10240 cores
  • Possibly RT improvements
  • Sources

AMD RDNA 3

  • Release Date: late 2021 or 2022
  • “Advanced Node”, probably TSMC 6 nm or 5 nm
  • Big focus is power efficiency
  • Sources

Intel DG2 discrete GPU

  • Release Date: 2021, possibly H2
  • Successor to DG1 Intel Xe discrete GPU
  • 512 EUs, or roughly 4096 classic shaders
  • 8 GB GDDR6 memory
  • Probably produced at TSMC, possibly 7 nm
  • Sources

Intel Ponte Vecchio [updated]

  • Release Date: 2021 or 2022
  • Discrete GPU
  • Produced on 7 nanometer production process
  • Probably not 7 nanometer Intel but 7 nm TSMC or even 6 nm TSMC
  • Multiple GPU dies will be combined into a single accelerator
  • Architected “for HPC modeling and simulation workloads and AI training”
  • Workloads can be processed by GPU and CPU at the same time, using Intel oneAPI
  • Foveros packaging technology
  • Xe link to combine multiple GPUs (CXL interconnect)
  • Xe HPC photo suggests that there’s two types of memory on the interposer, one of them being HBM
  • Sources

Intel Jupiter Sound

  • Release Date: 2022
  • Discrete GPU
  • Produced on 10 nanometer production process
  • Successor to Arctic Sound
  • Sources

Zhaoxin Discrete GPU

  • Release Date: unknown
  • Discrete GPU
  • Produced on 28 nanometer production process
  • 70 Watt TDP
  • Based on VIA S3 graphics IP
  • Sources

Chipsets

Intel 500 Series Chipsets

  • Release Date: 2021, possibly March
  • For Rocket Lake processors
  • Models: Z590 (overclockers), H570 (premium desktop), B560 (midrange desktop), H510 (entry-level desktop), Q570 (commercial desktop), W580 (workstation)
  • BIOSTAR: Z590 Valkyrie and Z590I Valkyrie
  • Socket LGA1200
  • PCI-Express 4.0
  • 8-lane DMI 3.0 chipset bus between the processor and the PCH
  • 2.5 Gb/s Ethernet, Thunderbolt 4, USB 3.2 20G
  • Sources

Memory

DDR5 System Memory

  • Release Date: probably 2021
  • JEDEC standard finalized as of Jul 15th 2020
  • Demo’d in May 2018 by Micron: DDR5-4400
  • Samsung 16 Gb DDR5 DRAM developed since February 2018
  • Samsung has completed functional testing and validation of a LPDDR5 prototype: 10 nm class, 8 Gbit, final clocks: DDR5-5500 and DDR5-6400
  • Samsung has started 16 Gb LPDDR5 mass production in Aug 2020
  • SK Hynix 4800 – 5600 Mbps, 1.1 V
  • SK Hynix also has 16 Gb DDR5-5200 samples ready, 1.1 V, mass production expected 2020
  • April 2020: Hynix has 8.4 Gbps DDR5, minimum density per die is 8 Gbit, maximum is 64 Gbit
  • ECC is now supported by all dies (no longer specific to server memory modules)
  • SK Hynix demonstrated DDR5 RDIMM modules at CES 2020: 4800 MHz, 64 GB
  • Micron is shipping LPDDR5 for use in Xiaomi phones (Feb 2 2020); 5.5 Gbps and 6.4 Gbps
  • Samsung has begun production for LPDDR5 for mobile devices (Feb 25 2020); 16 GB, 5.5 Gbps
  • ADATA: up to 8400 MT/s and up to 64 GB
  • 4800–6400 Mbps
  • Expected to be produced using 7 nm technologies
  • 32 banks, 8 bank groups
  • 64-bit link at 1.1 V
  • Burst length doubled to BL16
  • Bank count increased from 16 to 32
  • Fine grain refresh feature
  • Improved power efficiency enabled by Vdd, going from 1.2 V to 1.1 V as compared to DDR4
  • On-die ECC
  • Voltage regulators on the DIMM modules
  • AMD DDR5 memory support by 2021/2022, with Zen 4
  • Sources

HBM2E Graphics Memory

  • Release Date: 2020
  • Used on products: 2021
  • Offers 3.2 Gbps per pin (33% faster than HBM2)
  • Rambus offers a 4.0 Gbps memory interface controller
  • Samsung Flashbolt: 16 Gb per die, 8-layers stacked, 16 GB per chip with 410 GB/s bandwidth
  • Hynix: 460 GB/s, 3.6 Gbps, eight 16 Gb chips are stacked for a single 16 GB chip
  • Hynix: mass production has started as of July 2020
  • Sources

HBM3 Graphics Memory

  • Release Date: originally “not before 2019”, no updated timing is known
  • Double the memory bandwidth per stack (4000 Gbps expected)
  • Expected to be produced using 7 nm technologies
  • Sources

HBMNext Memory

  • Release Date: late 2022 or 2023
  • JEDEC work in progress
  • Micron involved
  • Sources

Silicon Fabrication Tech

TSMC 7 nanometer+

  • Release Date: Q4 2019
  • TSMC N7+ is successor to original 7 nm node
  • Uses EUV (Extreme Ultra Violet)
  • 15–20% more density and improved power consumption over N7
  • Sources

TSMC 6 nanometer

  • Release Date: unknown
  • Backwards compatible with 7 nm process—no new design tools needed
  • Uses EUV (Extreme Ultra Violet), up to four EUV layers
  • 18% higher logic density than N7
  • Sources

TSMC 5 nanometer

  • Release Date: March 2020 to tape-out customer designs
  • Risk production as of Q2 2019
  • High volume production: Q2 2020
  • Uses TSMC’s second implementation of EUV (Extreme Ultra Violet)
  • Up to 1.8x the density of 7 nm
  • Up to 14 layers
  • +15% higher clocks
  • 30% better bower than N7
  • Intel might be a customer of this node
  • N5P “Plus” node: improvement to N5 while staying on 5 nm, 84–87% increase in transistor densities over N7
  • Sources

TSMC 5 nanometer+

  • Release Date: 2021
  • High-volume production in Q4 2020
  • Uses EUV (Extreme Ultra Violet)
  • Sources

TSMC 4 nanometer

  • Mass production: 2023
  • Codename “N4”
  • Uses EUV lithography
  • Sources

TSMC 3 nanometer

  • April 2020: on track
  • Risk production: 2021
  • Volume production: H2 2022
  • FinFET technology
  • Uses TSMC’s third implementation of EUV (Extreme Ultra Violet)
  • 10–15% speed improvement at iso-power or 25–30% power reduction at iso-speed, compared to N5.
  • 55,000 water per month at the start, 100,000 by 2023
  • 12-inch wafer size
  • Sources

TSMC 3 nanometer+

  • Release date: 2023
  • First client will be Apple
  • Sources

TSMC 2 nanometer

  • Release Date: 2023 (risk production)
  • June 2020: TSMC is accelerating R&D
  • Sep 2020: fab construction has begun
  • Will use Gate-All-Around (GAA) technology
  • Multi-bridge channel field effect transistor (MBCFET) architecture
  • Sources

Samsung 6 nanometer

  • Release Date: unknown
  • First product taped out as of Q2 2019
  • Uses EUV (Extreme Ultra Violet)
  • Special variant for customers
  • Sources

Samsung 5 nanometer

  • Release Date: 2020
  • Ready for customer sample production as of Q2 2019
  • In production as of Q4 2020
  • Yields are challenging as of Q2 2020
  • Uses EUV (Extreme Ultra Violet)
  • Up to 25% the density of 7 nm
  • 20% lower power consumption
  • 10% higher performance
  • Sources

Samsung 3 nanometer

  • Release Date: 2022
  • 50% less power while delivering 30% more performance
  • 45% less silicon space taken per transistor (vs. 7 nm)
  • Sources

Intel 7 nanometer [updated]

  • Release Date: 2023
  • Succeeded by 7 nm+ node in 2022, and 7 nm++ in 2023
  • Uses EUV (Extreme Ultra Violet)
  • 4x reduction in design rules
  • Planned to be used on multiple products: CPU, GPU, AI, FPGA, 5G networking
  • Jan 2021: Intel reports “issues fixed”
  • Sources

Other

Hynix 4D NAND

  • Release Date: H1 2019
  • Developed by SK Hynix
  • Sampling in Q4 2018
  • Products demonstrated at CES 2020: Platinum P31 M.2 NVMe and Gold P31—PCIe 3.0 x4, using flash, DRAM, and controller made by Hynix, over 3 GB/s read/write.
  • Reduces chip physical size while increasing capacity
  • Supports TLC and QLC
  • 30% higher write and 25% higher read performance
  • 1.2 V
  • 1st generation: 96 stacks, 1.2 Gbps per pin, 512 Gbit TLC
  • 128 stacks in development, scales up to 512 stacks
  • Sources

Toshiba 5-Bit-per-Cell NAND Flash (PLC)

  • Release Date: unknown
  • Stores an additional bit of information per cell (compared to QLC)
  • 32 states per cell
  • Will enable even cheaper SSDs, probably with a performance cost
  • Sources

Toshiba XL-Flash

  • Developed by Toshiba
  • Uses existing SLC flash technology to improve latencies
  • 1/10th the read latency of TLC
  • Good for random IOPS and better QoS at shallow queue depth
  • Can combine SLC and TLC/QLC for tiered, cost-optimized storage
  • Intel Optane memory competitor
  • 128 gigabit (Gb) die (in a 2-die, 4-die, 8-die package)
  • 4 KB page size for more efficient operating system reads and writes
  • 16-plane architecture for more efficient parallelism
  • Fast page read and program times
  • Sources

Micron 128-layer 3D NAND Flash

  • Release Date: 2020, taped out as of Q4 2019
  • CMOS-under-array design, but with Replacement Gate (RG) Technology instead of Floating Gate
  • Only for few applications, more focused on next-generation RG tech, which brings down cost, too
  • Sources

Micron 176-layer 3D NAND Flash

  • Release Date: Nov 2020 (volume shipments)
  • CMOS-under-array design
  • 30% smaller die size
  • 35% improved read/write latency
  • 1600 MT/s transfer rate
  • Sources

Hynix 176-layer 3D NAND Flash

  • Release Date: 2020
  • 512 Gbit TLC
  • 20% faster read speed per cell
  • 1600 MT/s transfer rate
  • Sources

Toshiba 128-layer 3D NAND Flash

  • Release Date: 2020 or 2021
  • Developed by Toshiba and partner Western Digital
  • Called BiCS 5
  • According to a press release in Feb 2020, this is actually a 112 layer stacking process
  • Cells are TLC (not QLC)
  • Chip density: 512 Gb
  • Write performance per channel doubled to 133 MB/s
  • Sources

Intel 144-layer 3D NAND Flash

  • Release Date: 2020
  • Supports QLC, but can be configured to work as TLC or SLC
  • SSD codename “Keystone Harbor”
  • PLC (5-bit per cell) technology development is underway
  • Optane product codename “Alder Stream”, PCIe Gen4
  • Sources

SK Hynix 128-layer 3D NAND Flash

  • Mass Production: July 2020
  • Up to 1 Tb TLC flash per chip
  • Data rate up to 1400 Mbps at 1.2 V
  • Products will be 2 TB client SSD with in-house controller and 16 TB / 32 TB NVMe datacenter SSDs.
  • Sources

Samsung 160-layer 3D NAND Flash

  • Release Date: end of 2020
  • 7th generation V-NAND
  • Sources

Intel CXL Interconnect

  • New interconnect for high-bandwidth devices like GPUs
  • Targeted at enterprise and servers
  • Competitor to NVLink, Infinity Fabric and PCI-Express
  • Uses PCIe physical layer
  • Link layer designed for low latency
  • 32 Gbps per lane, per direction (like PCIe Gen 5.0)
  • Sources

PCI-Express 5.0

  • Specification released end of May 2019
  • Products not expected before 2020
  • 32 GT/s bandwidth per lane, per direction (4x the bandwidth of PCIe 3.0)
  • 128/130 bit encoding (= 1.5% overhead)
  • Implements electrical changes to improve signal integrity and mechanical performance of connectors
  • Physical connector is backward compatible
  • Signalling is backward compatible with all previous PCIe versions
  • Sources

PCI-Express 6.0

  • Specification targeted for 2021
  • Spec version 0.5 published as of Feb 2020
  • Spec version 0.7 published as of Nov 2020
  • 64 GT/s raw bit rate, up to 256 GB/s with x16
  • Includes low-latency Forward Error Correction (FEC) with additional mechanisms to improve bandwidth efficiency
  • Maintains backwards compatibility with all previous generations of PCIe technology
  • New physical layer with PAM4 (pulse amplitude modulation) signaling replacing NRZ (non-return to zero)
  • Sources

USB 4.0

  • Release Date: end of 2020
  • Specification Released: September 2019
  • Conceptually similar to Thunderbolt 3
  • Up to 40 Gbps speeds using two-lane operation
  • Multiple data and display protocols can share bandwidth
  • Uses USB Type-C connector
  • Backwards compatible with USB 2.0, 3.0, 3.1, 3.2, and Thunderbolt 3
  • Resulting connection scales to the best mutual capability of the devices being connected
  • Sources